1. Field of the Invention
This invention relates generally to flip chip packaging technology and even more specifically, this invention relates to chip scale flip chip packaging technology for semiconductor die.
2. Discussion of the Related Art
Chip Scale Packages (CSP) for semiconductor die currently embody some form of solder ball or bump to attach the die to the next higher assembly in the total package. In the simplest form of a CSP, the CSP is a flip chip semiconductor die that has additional solder bumps to be connected to normal bond pads on a substrate which are used to wire bond interconnects to a package or substrate. The semiconductor die is inverted and the solder is reflow melted which structurally attaches the die to the metallized pads or to traces on the substrate.
The solder-bump flip-chip interconnection technology was initiated in the early 1960s to eliminate the expense, unreliability, and low productivity of manual wirebonding. The so-called controlled-collapse-chip connection C4 or C4 utilizes solder bumps deposited on wettable metal terminals on the chip which are joined to a matching footprint of solder wettable terminals on the substrate. The upside-down chip (flip chip) is aligned to the substrate and all joints are made simultaneously by reflowing the solder.
The most recent innovations to the flip chip technology involve the relocation of the solder ball/bump sites from the close pitch pads which are normally placed around the perimeter of the semiconductor die to an array located across the surface of the die. This is accomplished by creating new traces from the perimeter locations to the new array locations on top of a passivation layer. The passivation layer is typically a glass protective layer deposited on the surface of the die with openings to expose the bond pads or by adding an interposer connector, which is bonded to the existing pads and reroutes traces to the array. An interposer connector is a connector structure that is routed between two parts to be connected.
A current interposer connector process reroutes connectors to the pads by extending them into the space between adjacent die as created on the semiconductor wafer, laminating a piece of glass to either side of the wafer and then through a complex series of mechanical cutting, metal deposition and etching operations, the connectors to the pads are extended to the surface of the glass. This produces an array on the top of the glass sheet covering the die, which is in turn adhesively bonded to the passivation surface of the die. The advantage of this process and structure is that the glass sheet provides a protective surface for the delicate surface of the passivated die and allows some degree of differential expansion between the die surface and the array of solder balls due to the non rigid nature of the adhesive layer. The disadvantages are that the extension of the connectors to the pads on the wafer are difficult to implement and often prevent the process from being possible, the glass cutting operation is costly and requires special equipment, the process is implemented on a completed semiconductor wafer which is very sensitive and costly and any error causes the entire wafer to be scrapped, and two sheets of glass are always required.
Therefore, what is needed is a chip scale flip chip process that is easy to implement, uses one glass sheet and is inexpensive.